The present invention relates to semiconductor devices of MIS type (insulated gate type), such as a lateral power MOSFET, having a main current path in the lateral direction thereof. More specifically, the present invention relates to a semiconductor device structure that facilitates the stabilization of breakdown voltage of the semiconductor device and lowering the on-resistance thereof.
The so-called lateral power MOSFET, which has a main current path in the lateral direction thereof, is manufactured by planar diffusion from the surface of a semiconductor substrate. The lateral power MOSFET is characterized in that the lateral power MOSFET employs a reduced surface electric field (RESURF) technique and other such techniques to expand the depletion layer in the lateral direction thereof. This is caused by a reverse bias voltage applied between the source and the drain of the lateral power MOSFET, so that a certain breakdown voltage may be secured. Since the lateral power MOSFET is manufactured through a typical IC process, monolithic power IC""s, having a control circuit and lateral power MOSFET""s integrated therein, have been placed on the market.
FIG. 19 is a cross sectional view of a conventional n-channel lateral power MOSFET (hereinafter referred to as a xe2x80x9cfirst conventional power MOSFETxe2x80x9d) disclosed in U.S. Pat. No. 4,811,075. Referring to FIG. 19, the first conventional lateral power MOSFET includes a highly resistive p-type substrate 101, having of resistivity is of about 125 ohm-cms; an n-type offset region 103 in the surface portion of p-type substrate 101; a p-type base region 102 in the surface portion of p-type substrate 101, base region 102 including (1) an n+-type source region 105 in the surface portion thereof and (2) a channel portion in the extended portion thereof, extending between source region 105 and n-type offset region 103; a p-type offset region 104 in the surface portion of n-type offset region 103, the potential of the p-type offset region 104 being fixed at the source potential; an n+-type drain region 106 in the surface portion of n-type offset region 103, the n+-type drain region 106 being spaced apart from n+-type source region 105 for about 80 micrometers; a field oxide film 108 on p-type offset region 104; a gate oxide film 107 on the channel portion of base region 102; a gate electrode 109 on gate oxide film 107; a source electrode 111 on source region 105; a drain electrode 112 on drain region 106; an interlayer film 113; and a protection film 114. The n-type offset region 103 is extended toward source region 105. A p+-type region is disposed on base region 102 to secure ohmic contact for base region 102.
When a reverse bias voltage is applied between source electrode 111 and drain electrode 112, a depletion layer expands from the pn-junction between substrate 101 and n-type offset region 103 and another depletion layer from the pn-junction between n-type offset region 103 and p-type offset region 104. The first conventional power MOSFET is configured such that two depletion layers expand in a well-balanced manner and join each other to relax the electric field and, thereby, to secure a high breakdown voltage. Equipotential curves at an applied voltage of 750 V are shown in FIG. 19, at intervals of every 150 V.
Usually, actual lateral power MOSFET products are packaged in a plastic mold. Ionic particles (ions 105 or electric charges) in the plastic mold of a lateral power MOSFET cause unfavorable phenomena as described below.
When high voltage is applied between the source and the drain of the lateral power MOSFET packaged in a plastic mold, especially at high temperatures, positive ions 115a and positive electric charges in the plastic mold are attracted toward source electrode 111, and negative ions 115b and negative electric charges in the plastic mold are attracted toward drain electrode 112. As a result, in the portion to which the positive ions 115a and positive electric charges are attracted, protection film 114, interlayer film 113 and field oxide film 108 constitute a capacitor. On the substrate side thereof, negative electric charges 115c are induced, as shown in FIG. 20. The induced negative electric charges 115c turn a part of p-type offset region 104 to an n-type. In the portion to which the negative ions 115b and negative electric charges are attracted, positive electric charges 115d are induced, as shown in FIG. 20. The induced positive electric charges 115d thicken a portion of p-type offset region 104. Therefore, the original p-type offset region 104 deforms to a p-type offset region 104a. The deformation of the p-type offset region 104 causes an imbalance between the expanding depletion layers, a strong electric field locally, and lowers the breakdown voltage between the source and the drain.
In the first conventional lateral power MOSFET of FIG. 19, the main current path between the source and the drain is n-type offset region 103 in the ON-state. However, since p-type offset region 104 is formed in the surface portion of n-type offset region 103 to promote depletion at reverse bias voltage application, the main current path is pinched off easily (JFET effect) as the drain voltage rises and, thereby, the on-resistance is increased.
FIG. 21 is a cross sectional view showing a second conventional lateral power MOSFET and equipotential curves therein. The second conventional lateral power MOSFET has a structure that omits the p-type offset region 104 from the first conventional lateral power MOSFET of FIG. 19. Since there exits no p-type offset region in the second conventional lateral power MOSFET, the main current path thereof is hardly pinched off. As a result, the on-resistance thereof is suppressed at a low value. However, since a pn-junction is formed only between the p-type substrate and the n-type offset region, the n-type offset region is not easily depleted when a reverse bias voltage is applied. The breakdown voltage of the second conventional lateral power MOSFET is about 450 V, which is lower than that of the first conventional lateral power MOSFET.
Two problems of the conventional lateral power MOSFET""s described above will now be summarized. First, when high voltage is applied at a high temperature between the source and the drain of the first conventional lateral power MOSFET packaged in a plastic mold, ions and electric charges in the plastic mold are attracted toward the source electrode and the drain electrode, and are localized thereon. The localized ions and electric charges induce electric charges of opposite polarities on the substrate side of the capacitor formed by the protection film and such other constituents. The induced electric charges deform the p-type offset region, cause an imbalance of depletion, and lower the breakdown voltage between the source and the drain.
Secondly, in the first conventional lateral power MOSFET, since the main current path in the ON-state is the n-type offset region between the p-type substrate and the p-type offset region, the main current path is easily pinched off as the drain voltage rises and the on-resistance is increased. In the second conventional lateral power MOSFET that omits the p-type offset region from the first conventional lateral power MOSFET, the n-type offset region is not easily depleted at reverse bias voltage application. Thus, the breakdown voltage is lowered.
In view of the foregoing, it is an object of the invention to provide a semiconductor device, manufactured at low manufacturing cost, that obviates the problems described above and prevents the lowering of the breakdown voltage.
According to a first aspect of the present invention, there is provided a semiconductor device having a MIS structure, the semiconductor device including: a semiconductor substrate of a first conductivity type; a base region of the first conductivity type formed selectively in the surface portion of the semiconductor substrate; a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate; a heavily doped source region of the second conductivity type formed selectively in the surface portion of the base region; a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region; a gate insulation film at least on the extended portion of the base region extended between the source region and the offset region; a gate electrode on the gate insulation film; a source electrode on the source region; a drain electrode on the drain region; a field insulation film formed selectively on the offset region; and a spiral thin film on the field insulation film. An end of the spiral thin film is connected to the drain electrode, and another end of the spiral thin film is connected to the source electrode. The spiral thin film is formed of multiple pn-diodes connected in series and surrounds the drain electrode.
According to a second aspect of the invention, there is provided a semiconductor device having a MIS structure, the semiconductor device including: a semiconductor substrate of a first conductivity type; a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate; a base region of the first conductivity type formed selectively in the surface portion of the offset region; a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region, the drain region being spaced apart from the base region; a source region of the second conductivity type formed selectively in the surface portion of the base region; a gate insulation film at least on the extended portion of the base region extended between the source region and the offset region; a gate electrode on the gate insulation film; a source electrode on the source region; a drain electrode on the drain region; a field insulation film formed selectively on the offset region; and a spiral thin film on the field insulation film. One end of the spiral thin film is connected to the drain electrode, and another end of the spiral thin film is connected to the source electrode. The spiral thin film being formed of multiple pn-diodes connected in series and surrounds the drain electrode.
Advantageously, the semiconductor device further includes a counter-doped region in the surface portion of the offset region. The counter-doped region is formed by diffusing impurities of the first conductivity type to the surface portion of the offset region at such a concentration that the counter-doped region is of the second conductivity type.
Also advantageously, the semiconductor device further includes a counter-doped region in the surface portion of the offset region between the source region and the drain region. The counter-doped region is formed by diffusing impurities of the first conductivity type to the surface portion of the offset region at such a concentration that the counter-doped region is of the second conductivity type.
Further still, the semiconductor device advantageously includes an offset region of the first conductivity type formed selectively in the surface portion of the offset region of the second conductivity type. Still further, the semiconductor device advantageously includes an offset region of the first conductivity type formed selectively in the surface portion of the offset region of the second conductivity type between the source region and the drain region.
Preferably, the semiconductor device includes a resistor thin film replacing the thin film formed of multiple pn-diodes connected in series. Also, preferably, one or more turns of the spiral thin film are between the drain electrode and the source electrode. Further, the spiral thin film is preferably made of polysilicon. Further still, the product of the reverse blocking voltage value of one of the pn-diodes and the number of the pn-diodes is preferably larger than the breakdown voltage between the source region and the drain region of the semiconductor device.
In a particularly preferred embodiment, the semiconductor device further includes one or more spiral thin films. Also preferably, the spiral thin film includes a thin film resistor branching from the midpoint of series connection of the pn-diodes, the thin film resistor being formed along the drain electrode and the source electrode. Preferably, the thin film resistor employs the p-type layer or the n-type layer of the pn-diodes. The spiral polysilicon thin film on the field plate between the source and drain electrodes may be formed of multiple pn-diodes connected in series, a highly resistive thin film of more than several M-ohms, or multiple pn-diodes and a highly resistive thin film. The semiconductor device may include one or more spiral polysilicon thin films.
When a reverse bias voltage is applied between the source and the drain, the reverse saturation current of the pn-diodes or a resistance current flows through the spiral thin film and, as a result, an almost uniform potential gradient is obtained across the thin film.
In a practical device, the thin film, arranged on a field oxide plate, having a certain width and spirally wound with a certain spacing between adjacent turns, works as a field plate, the local potential thereof changing with every turn. Since the local potential of the substrate beneath a specific position of the spiral thin film is forced to close to the local potential of the spiral thin film at the specific position due to the field plate effect, the potential gradient across the depletion layer is almost uniform. Moreover, since the spiral thin film exhibits shield effects against disturbances such as ions and electric charges in the plastic mold of the semiconductor device, deviations of the breakdown voltage are significantly reduced, even when high voltage is applied at a high temperature. Thus, a very reliable semiconductor device is obtained.
Since the spiral polysilicon thin film works as a field plate, the impurity concentration in the p-type offset region, which increases on-resistance, may be lower than the optimum concentration, in that a certain breakdown voltage is secured without providing the polysilicon thin film. FIG. 22 shows a set of curves relating the breakdown voltage and the on-resistance with the p-type impurity concentration in the surface portion of the n-type offset region, in which the n-type impurity concentration is 3xc3x971016cmxe2x88x923. FIG. 23 shows a set of curves relating the breakdown voltage and the on-resistance with the p-type impurity concentration in the surface portion of the n-type offset region, in which the n-type impurity concentration is 7xc3x971015 cmxe2x88x923. In these figures, xe2x80x9cBvdss xe2x80x9d represents the breakdown voltage, and xe2x80x9cRonxe2x80x9d represents the on-resistance. xe2x80x9cBvdss(w/o PF)xe2x80x9d represents the breakdown voltage of the conventional device not including any spiral thin film. xe2x80x9cBvdss(w PF)xe2x80x9d represents the breakdown voltage of the device including a spiral thin film according to the invention.
FIG. 23 indicates that a desired breakdown voltage may be obtained by diffusing p-type impurities to the surface portion of the n-type offset region at a concentration that does not turn the surface portion of the n-type offset region into a p-type. Moreover, when the n-type offset region is doped more lightly and shallower (the case shown in FIG. 23), a desired breakdown voltage is secured without providing any p-type offset region. In other words, the spiral polysilicon thin film facilitates decreasing the concentration of the p-type offset region, which increases the on-resistance, substantially reducing the resistance of the p-type offset region and producing a semiconductor device exhibiting low on-resistance.
The saturation current of the pn-diodes and/or the current flowing through the thin film resistor, caused when a reverse bias voltage is applied between the source electrode and the drain electrode, facilitates obtaining an almost uniform potential gradient across the spiral thin film formed on the field oxide film between the source electrode and the drain electrode. The local potential of the substrate is equalized with the local potential of the spiral thin film, thus producing a stable breakdown voltage.
Moreover, since the spiral thin film exhibits shield effects against disturbances such as ions and electric charges in the plastic mold of the semiconductor device, deviations of the breakdown voltage hardly occur, even when high voltage is applied at a high temperature. Thus, a very reliable semiconductor device is obtained. Since the spiral polysilicon thin film works as a field plate, the impurity concentration in the p-type offset region, which increases on-resistance, may be lower than the optimum concentration. Under these conditions, a certain breakdown voltage is secured without needing to provide the polysilicon thin film.
Since the resistance of the n-type offset region, which provides a main current path in the ON-state of the semiconductor device, is substantially reduced, the on-resistance of the semiconductor device is reduced. In detail, FIGS. 22 and 23 indicate that the onresistance may be reduced by about 40%. Since the area of the power MOSFET may be reduced by about 40% for the same on-resistance values, the cost of the semiconductor device is greatly reduced.
According to a third aspect of the invention, there is provided a semiconductor device having a MIS structure, the semiconductor device including: a semiconductor substrate of a first conductivity type; a base region of the first conductivity type formed selectively in the surface portion of the semiconductor substrate; a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate; a heavily doped source region of the second conductivity type formed selectively in the surface portion of the base region; a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region; a gate insulation film at least on the extended portion of the base region extended between the source region and the offset region; a gate electrode on the gate insulation film; a source electrode on the source region; a drain electrode on the drain region; a field insulation film formed selectively on the offset region; a first thin film formed of pn-diodes connected in series; a first thin resistive layer; and a second thin film formed of pn-diodes connected in series, with the source electrode surrounding the drain electrode or the drain electrode surrounding the source electrode. One end of the first thin film is connected to the source electrode, and another end is connected to an end of the first thin resistive layer. One end of the first thin resistive layer is connected to an end of the second thin film, and another end of the second thin film is connected to the drain electrode.
Advantageously, the semiconductor device further includes an interlayer insulation film and connection holes, with the interlayer insulation film being on the first thin film and the second thin film; the first thin resistive layer being on the interlayer insulation film; the connection holes being bored through the interlayer insulation film on intermediate ones of the pn-diodes in the first thin film and the second thin film; the intermediate ones of the pn-diodes in the first thin film and the second thin film being connected to the first thin resistive layer through the connection holes; and the first thin resistive layer being formed along the source electrode or the drain electrode.
Also advantageously, the source electrode includes an extended portion extended from the source region, and the drain electrode includes an extended portion extended from the drain region. The extended portions of the source electrode and the drain electrode are preferably above the first thin resistive layer. One end of the first thin film is preferably connected to the source electrode in the vicinity of the source region, such as a gate electrode, and an end of the second thin film is connected to the drain electrode in the vicinity of the drain region.
Advantageously, the first thin resistive layer is made of polysilicon with low electrical resistance. Also advantageously, the first thin resistive layer is an aluminum resistive film.
Preferably, the semiconductor device further includes an interlayer insulation film and a second thin resistive layer, with the interlayer insulation film being on the first thin film, the second thin film, and the first thin resistive layer. The source electrode and the drain electrode are preferably on the interlayer insulation film, and the second thin resistive layer is preferably in the portion of the interlayer insulation film between the source electrode and the drain electrode.
Further, the source electrode advantageously includes an extended portion extending from the source region; the drain electrode includes an extended portion extending from the drain region; and the extended portions of the source electrode and the drain electrode are above the second thin resistive layer. One end of the first thin film is connected to the source electrode in the vicinity of the source region, such as a gate electrode, and an end of the second thin film is connected to the drain electrode in the vicinity of the drain region.
Further still, the semiconductor device advantageously includes connection holes, through which the second thin resistive layer is connected to the first thin film and the second thin film or to the first thin resistive layer.
Still further, the side face of the source electrode preferably has straight sections and semicircular sections, and the side face of the drain electrode has straight sections and semicircular sections. The straight sections of the source electrode and the straight sections of the drain electrode are advantageously facing opposite each other, and the semicircular sections of the source electrode and the semicircular sections of the drain electrode are facing opposite each other. The first thin resistive layer preferably has a semicircular section between the semicircular section of the source electrode and the semicircular section of the drain electrode, and the width of the semicircular section of the first thin resistive layer in the central portion thereof is preferably wider than the width of the semicircular section of the first thin resistive layer in the end portions thereof.
According to a fourth aspect of the invention, there is provided a semiconductor device including: a semiconductor substrate of a first conductivity type; a base region of the first conductivity type formed selectively in the surface portion of the semiconductor substrate; a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate; a heavily doped source region of the second conductivity type formed selectively in the surface portion of the base region; a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region; a gate insulation film at least on the extended portion of the base region extending between the source region and the offset region; a gate electrode on the gate insulation film; a source electrode on the source region; a drain electrode on the drain region; a field insulation film formed selectively on the offset region; a first thin film formed of pn-diodes connected in series; a thin resistive layer; and a second thin film formed of pn-diodes connected in series. Preferably, the source electrode surrounds the drain electrode, or the drain electrode surrounds the source electrode. The thin resistive layer is preferably between the source electrode and drain electrode, the thin resistive layer turning around along the source electrode and drain electrode. An end of the first thin film is preferably connected to the source electrode, and another end of the first thin film is connected to a first location of the thin resistive layer. An end of the second thin film is preferably connected to a second location of the thin resistive layer, and another end of the second thin film being connected to the drain electrode.
Advantageously, the side face of the source electrode has straight sections and semicircular sections; the side face of the drain electrode has straight sections and semicircular sections; the thin resistive layer has straight sections and semicircular sections; the straight sections of the source electrode and the straight sections of the drain electrode are facing opposite each other; the semicircular sections of the source electrode and the semicircular sections of the drain electrode are facing opposite each other; the semicircular section of the thin resistive layer is between the semicircular section of the source electrode and the semicircular section of the drain electrode; and the width of the semicircular sections of the thin resistive layer in the central portion thereof is wider than the width of the semicircular sections of the thin resistive layer in the end portions thereof.
Advantageously, the thin resistive layer is made of polysilicon with low electrical resistance. Also advantageously, the thin resistive layer is an aluminum resistive film.
The parasitic capacitance is reduced by disposing a thin resistive layer above the thin film of pn-diodes and by connecting the thin resistive layer to the intermediate one of the pn-diodes connected in series. The central portion of the thin resistive layer is widened more than the end portion to suppress the influence of ions in a plastic mold. The undesirable influence of these ions is greatly reduced by extending the source electrode and the drain electrode above the thin resistive layer.